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Wires as interconnects
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2005 (English)In: Interconnect-Centric Design for Advanced SoC and NoC, Springer, 2005, 25-54 p.Chapter in book (Refereed)
Abstract [en]

Deep submicron technology is rapidly leading to exceedingly complex, billiontransistor chips. This has resulted in a new circuit paradigm—system-on-chip (SoC). However, deep submicron physics indicates that wires, not transistors, dominate power and performance. Interconnects have been a key design objective in deep submicron SoC. In this chapter, we review interconnect performance as technologies migrate from 0.25μm to 0.035μm feature sizes. Challenges of deep submicron effects and their impacts on advanced chip design are summarized. Basic concepts of signal integrity and various noise sources in deep submicron SoC are illustrated. Finally, interconnect strategies and interconnect-centric design methodologies are generally described; various design techniques for signal and power integrity in deep submicron SoC are discussed.

Place, publisher, year, edition, pages
Springer, 2005. 25-54 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-73955DOI: 10.1007/1-4020-7836-6_2Scopus ID: 2-s2.0-80054994468ISBN: 978-1-4020-7835-4 (print)ISBN: 978-1-4020-7836-1 (electronic)OAI: oai:DiVA.org:kth-73955DiVA: diva2:489086
Note

QC 20120202

Available from: 2012-02-02 Created: 2012-02-02 Last updated: 2017-04-04Bibliographically approved

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  • apa
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