Wires as interconnects
2005 (English)In: Interconnect-Centric Design for Advanced SoC and NoC, 25-54 p.Article in journal (Refereed) Published
Deep submicron technology is rapidly leading to exceedingly complex, billiontransistor chips. This has resulted in a new circuit paradigm—system-on-chip (SoC). However, deep submicron physics indicates that wires, not transistors, dominate power and performance. Interconnects have been a key design objective in deep submicron SoC. In this chapter, we review interconnect performance as technologies migrate from 0.25μm to 0.035μm feature sizes. Challenges of deep submicron effects and their impacts on advanced chip design are summarized. Basic concepts of signal integrity and various noise sources in deep submicron SoC are illustrated. Finally, interconnect strategies and interconnect-centric design methodologies are generally described; various design techniques for signal and power integrity in deep submicron SoC are discussed.
Place, publisher, year, edition, pages
2005. 25-54 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-73955DOI: 10.1007/1-4020-7836-6_2ScopusID: 2-s2.0-80054994468OAI: oai:DiVA.org:kth-73955DiVA: diva2:489086
QC 201202022012-02-022012-02-022012-10-02Bibliographically approved