Nanocore/CMOS hybrid system-on-package (SoP) architecture for autonomous error-tolerant (AET) cellular array network
2005 (English)In: 2005 5th IEEE Conference on Nanotechnology, 2005, 353-356 p.Conference paper (Refereed)
In this paper, the nanocore/CMOS hybrid system-on-package (SoP) autonomous error-tolerant (AET) cellular network architecture, which integrates today’s mature CMOS technology with emerging nanotechnology, is proposed. Within the cellular network, each AET cell contains a nanocore, CMOS cell peripherals and their interface circuits in a silicon platform. The overall network is homogeneous. These imply strict constraints for intercellular connection schemes and routing policies. Depending on the communication requirement between two nodes.
Place, publisher, year, edition, pages
2005. 353-356 p.
Si; autonomous error-tolerant cellular array network; intercellular connection schemes; interface circuits; nanocore-CMOS hybrid system-on-package architecture; nanotechnology; silicon platform; CMOS integrated circuits; cellular arrays; fault tolerance; nanoelectronics; system-in-package;
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-73941DOI: 10.1109/NANO.2005.1500724ScopusID: 2-s2.0-33747018827OAI: oai:DiVA.org:kth-73941DiVA: diva2:489087
2005 5th IEEE Conference on Nanotechnology. Nagoya. 11 July 2005 - 15 July 2005
QC 201203142012-02-022012-02-022012-03-14Bibliographically approved