Nano scale autonomous error-tolerant (AET) cellular network
2005 (English)In: 2005 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2005 Technical Proceedings, 2005, 748-752 p.Conference paper (Refereed)
In this paper, the nano-CMOS hybrid Autonomous Error-Tolerant (AET) cellular network architecture, which integrates today's mature CMOS technology with emerging nanotechnology, is proposed. Within the cellular network, each AET cell contains a nanocore, CMOS cell peripherals and their interface circuits. The overall network is homogenous. These imply strict constraints for intercellular connection schemes and routing policies. Depending on the communication requirement between two nodes, different routing methods apply.
Place, publisher, year, edition, pages
2005. 748-752 p.
AET cell, Nano interconnect, Routing
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-73972ScopusID: 2-s2.0-32044434949ISBN: 0976798522OAI: oai:DiVA.org:kth-73972DiVA: diva2:489118
2005 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2005; Anaheim, CA; 8 May 2005 through 12 May 2005
QC 201202282012-02-022012-02-022012-02-28Bibliographically approved