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Nano scale autonomous error-tolerant (AET) cellular network
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
2005 (English)In: 2005 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2005 Technical Proceedings, 2005, 748-752 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, the nano-CMOS hybrid Autonomous Error-Tolerant (AET) cellular network architecture, which integrates today's mature CMOS technology with emerging nanotechnology, is proposed. Within the cellular network, each AET cell contains a nanocore, CMOS cell peripherals and their interface circuits. The overall network is homogenous. These imply strict constraints for intercellular connection schemes and routing policies. Depending on the communication requirement between two nodes, different routing methods apply.

Place, publisher, year, edition, pages
2005. 748-752 p.
Keyword [en]
AET cell, Nano interconnect, Routing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-73972Scopus ID: 2-s2.0-32044434949ISBN: 0976798522 (print)OAI: oai:DiVA.org:kth-73972DiVA: diva2:489118
Conference
2005 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2005; Anaheim, CA; 8 May 2005 through 12 May 2005
Note
QC 20120228Available from: 2012-02-02 Created: 2012-02-02 Last updated: 2012-02-28Bibliographically approved

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Liu, JianWeerasekera, RoshanZheng, Li-RongTenhunen, Hannu
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