Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks
2009 (English)In: PROCEEDINGS OF THE 2009 12TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, ARCHITECTURES, METHODS AND TOOLS, 2009, 141-146 p.Conference paper (Refereed)
A feasible and scalable per-core DVFS architecture for on-chip network is presented. The supplies are dynamically adjusted at a very fine granularity based on the local traffic status. The adoption of multiple voltage supply networks and power selecting transistors provides the architecture with scalability and feasibility superior to existing similar techniques. With high-level simulation using 65nm power model obtained from widely-acknowledged tools, the effectiveness of the technique is demonstrated with quantitative analysis of energy overhead and latency penalty. Under various traffic patterns, the average flit energy is reduced considerably, ranging from 45% to 60%, with moderately increased but stable transmission latency.
Place, publisher, year, edition, pages
2009. 141-146 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-74118DOI: 10.1109/DSD.2009.197ISI: 000275715100018ScopusID: 2-s2.0-74549167896OAI: oai:DiVA.org:kth-74118DiVA: diva2:489224
12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools. Patras, GREECE. AUG 27-29, 2009
QC 201202072012-02-022012-02-022016-05-09Bibliographically approved