A study of Through Silicon Via impact to 3D Network-on-Chip design
2010 (English)In: 2010 International Conference on Electronics and Information Engineering, ICEIE 2010, 2010, Vol. 1, V1333-V1337 p.Conference paper (Refereed)
The adoption of a 3D Network-on-Chip (NoC) design depends on the performance and manufacturing cost of the chip. Therefore, a study of Through Silicon Via (TSV), that connects different layers of a 3D chip, is crucial. In this paper, we analysis the impact of TSV design in 3D NoCs. A 3D NoC with five layers is modeled based on modern 2D chips. We discuss the TSV number required for a 3D NoC. Different placements of half and quarter layer-layer connections are explored. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average network latencies in full and half layer-layer connection are reduced by 5.24% and 2.18% respectively, compared with quarter design. Our analysis and experiment results provide a guideline for designing TSVs in 3D NoCs to leverage the trade-off between performance and manufacturing cost.
Place, publisher, year, edition, pages
2010. Vol. 1, V1333-V1337 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-74110DOI: 10.1109/ICEIE.2010.5559865ScopusID: 2-s2.0-78049343810OAI: oai:DiVA.org:kth-74110DiVA: diva2:489234
2010 International Conference on Electronics and Information Engineering, ICEIE 2010. Kyoto. 1 August 2010 - 3 August 2010
QC 201202072012-02-022012-02-022016-04-11Bibliographically approved