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A study of Through Silicon Via impact to 3D Network-on-Chip design
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
2010 (English)In: 2010 International Conference on Electronics and Information Engineering, ICEIE 2010, 2010, Vol. 1, V1333-V1337 p.Conference paper, Published paper (Refereed)
Abstract [en]

The adoption of a 3D Network-on-Chip (NoC) design depends on the performance and manufacturing cost of the chip. Therefore, a study of Through Silicon Via (TSV), that connects different layers of a 3D chip, is crucial. In this paper, we analysis the impact of TSV design in 3D NoCs. A 3D NoC with five layers is modeled based on modern 2D chips. We discuss the TSV number required for a 3D NoC. Different placements of half and quarter layer-layer connections are explored. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average network latencies in full and half layer-layer connection are reduced by 5.24% and 2.18% respectively, compared with quarter design. Our analysis and experiment results provide a guideline for designing TSVs in 3D NoCs to leverage the trade-off between performance and manufacturing cost.

Place, publisher, year, edition, pages
2010. Vol. 1, V1333-V1337 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-74110DOI: 10.1109/ICEIE.2010.5559865Scopus ID: 2-s2.0-78049343810OAI: oai:DiVA.org:kth-74110DiVA: diva2:489234
Conference
2010 International Conference on Electronics and Information Engineering, ICEIE 2010. Kyoto. 1 August 2010 - 3 August 2010
Note

QC 20120207

Available from: 2012-02-02 Created: 2012-02-02 Last updated: 2016-04-11Bibliographically approved

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  • apa
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  • de-DE
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  • en-US
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  • nn-NB
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  • Other locale
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