A study of 3d network-on-chip design for data parallel h. 264 coding
2011 (English)In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 35, no 7, 603-612 p.Article in journal (Refereed) Published
In this paper, we implement, analyze and compare different Network-on-Chip (NoC) architectures aiming at higher efficiencies for MPEG-4/H.264 coding. Two-dimensional (2D) and three-dimensional (3D) NoCs based on Non-Uniform Cache Access (NUCA) are analyzed. We present results using a full system simulator with realistic workloads. Experiments show the average network latencies in two 3D NoCs are reduced by 28% and 34% respectively, comparing with 20 design. It is also shown that heat dissipation is a trade-off in improving performance of 3D chips. Our analysis and experiment results provide a guideline to design efficient 3D NoCs for data parallel H.264 coding applications.
Place, publisher, year, edition, pages
2011. Vol. 35, no 7, 603-612 p.
Network-on-Chip, 3D IC design, H.264, Coding, Data parallel
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-74112DOI: 10.1016/j.micpro.2011.06.009ISI: 000297963000003ScopusID: 2-s2.0-80955131647OAI: oai:DiVA.org:kth-74112DiVA: diva2:489236
QC 201202072012-02-022012-02-022016-04-11Bibliographically approved