Operating system processor scheduler design for future chip multiprocessor
2010 (English)In: 2010 23rd International Conference on Architecture of Computing Systems (ARCS), 2010Conference paper (Refereed)
Today’s Chip Multiprocessor (CMP) designs are mainly based on the shared-bus communication architecture. However,as the scale of CMPs increase, this architecture suffers from high communication delay and power inefficiency. Therefore,network-on-chip (NoC) based architecture is proposed as a promising technique for future very large scale CMPs. Theoperating system (OS) scheduling is one of the most important design issues for CMP systems. In this paper, limitationsof state-of-the-art OS scheduler are discussed, with Sun Solaris used as a case study. The contribution of this paper lies inthe on-chip data traffic calculation of runtime applications. By evaluating FFT and SPECjbb as benchmarks, it is shownthat the Solaris scheduler does not provide the optimal communication scheme and thus suffers from the network latencyand overall performance degradation. We define a model for NoC-based CMP, based on which a scheduling algorithmis proposed to minimize communication latencies. The weights of memory access and inter process communication inscheduling are analyzed. A protocol for OS implementation of the algorithm has been proposed in this paper. Our analysisand experiment results provide a guideline for the designs of future multicore schedulers.
Place, publisher, year, edition, pages
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-74113OAI: oai:DiVA.org:kth-74113DiVA: diva2:489238
2010 23rd International Conference on Architecture of Computing Systems (ARCS). Hannover, Germany. 22-23 Feb. 2010
QC 201204242012-02-022012-02-022012-04-24Bibliographically approved