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An analysis of designing 2D/3D chip multiprocessor with different cache architecture
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2010 (English)In: NORCHIP, 2010, 2010Conference paper, Published paper (Refereed)
Abstract [en]

Network-on-Chip (NoC) has become a widely acceptedon-chip communication architecture which provides apromising solution to integrate a large number of components ona single chip. However, with the increasingly higher performancedemands for on-chip systems, NoCs are facing several criticalchallenges such as wire delay and power consumption. Therefore,in this paper, we explore different cache architecture designsin 2D/3D NoC architectures. Integrated core/cache and splitcore/cache architectures have been analyzed in terms of areaand wire delay. We present benchmark results using a cycleaccurate full system simulator. Experiments show that, by usingthe proposed 3D NoC architecture, compared with the integratedcore/cache design, the average network latency and average linkutilization are reduced by 5.01% and 26.07% respectively.

Place, publisher, year, edition, pages
2010.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-74105DOI: 10.1109/NORCHIP.2010.5669433Scopus ID: 2-s2.0-78751514067OAI: oai:DiVA.org:kth-74105DiVA: diva2:489240
Conference
NORCHIP, 2010. Tampere, Finland. 15-16 Nov. 2010
Note
QC 20120424Available from: 2012-02-02 Created: 2012-02-02 Last updated: 2012-04-24Bibliographically approved

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Tenhunen, Hannu
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