A Greedy Heuristic Approximation Scheduling Algorithm for 3D Multicore Processors
2011 (English)In: HPPC 2011: (Hand-out) Proceedings of the 5th Workshop onHighly Parallel Processingon a Chip, 2011, 38-47 p.Conference paper (Refereed)
In this paper, we propose a greedy heuristic approximationscheduling algorithm for future multicore processors. It is expected thathundreds of cores will be integrated on a single chip, known as a ChipMultiprocessor (CMP). To reduce on-chip communication delay, 3D integrationwith Through Silicon Vias (TSVs) is introduced to replace the2D counterpart. Multiple functional layers can be stacked in a 3D CMP.However, operating system process scheduling, one of the most importantdesign issues for CMP systems, has not been well addressed forsuch a system. We define a model for future 3D CMPs, based on whicha scheduling algorithm is proposed to reduce cache access latencies andthe delay of inter process communications (IPC). We explore differentscheduling possibilities and discuss the advantages and disadvantages ofour algorithm. We present benchmark results using a cycle accurate fullsystem simulator based on realistic workloads. Experiments show thatunder two workloads, the execution times of our scheduling in two configurations(2 and 4 threads) are reduced by 15.58% and 8.13% respectively,compared with the other schedulings. Our study provides a guideline fordesigning scheduling algorithms for 3D multicore processors.
Place, publisher, year, edition, pages
2011. 38-47 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-74107OAI: oai:DiVA.org:kth-74107DiVA: diva2:489242
HPPC 2011—the 5th Workshop on Highly Parallel Processing on a Chip, August 30, 2011, Bordeaux, France
QC 201204132012-02-022012-02-022012-04-13Bibliographically approved