Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip
2011 (English)In: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011, 2011, 105-110 p.Conference paper (Refereed)
In this paper, we analyze the performance impact of different number of Through Silicon Vias (TSVs) in 3D Network-on-Chip (NoC). The adoption of a 3D NoC design depends on the performance and manufacturing cost of the chip. Therefore, a study of the placement of the TSV, that connects different layers of a 3D chip, is crucial. A 64-core 3D NoC is modeled based on state-of-the-art 2D chips. We discuss the number of TSVs required for a 3D NoC. Different placements of layer-layer connections are explored. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average network latencies in two configurations (full and quarter connection) are reduced by 14.78% and 7.38% respectively, compared with the one-eighth connection design. The improvement of performance is a trade-off of manufacturing cost. Our analysis and experiment results provide a guideline for selecting optimal number of TSVs in 3D NoCs.
Place, publisher, year, edition, pages
2011. 105-110 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-74108DOI: 10.1109/DDECS.2011.5783057ScopusID: 2-s2.0-79959953294OAI: oai:DiVA.org:kth-74108DiVA: diva2:489243
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011. Cottbus. 13 April 2011 - 15 April 2011
QC 201202072012-02-022012-02-022016-04-11Bibliographically approved