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Exploring DRAM Last Level Cache for 3D Network-on-Chip Architecture
Department of Information, Technology,University of Turku.
2010 (English)In: Proceedings of the IEEE International Conference on Embedded System and Microprocessors, 2010, 39-44 p.Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
2010. 39-44 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-74109OAI: oai:DiVA.org:kth-74109DiVA: diva2:489245
Conference
2010 International Conference on Embedded System and Microprocessors,ICESM 2010. Manila, Philippines. December 4-5 2010
Note
QC 20120424Available from: 2012-02-02 Created: 2012-02-02 Last updated: 2012-04-24Bibliographically approved

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CiteExportLink to record
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  • apa
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