Analysis of delay variation in encoded on-chip bus signaling under process variation
2008 (English)In: 21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2008, 228-234 p.Conference paper (Refereed)
In this paper we model on-chip signaling over a bus consisting of encoding, drivers, transmission lines, receivers and decoding. We characterize the signaling circuitry as a function of its load capacitance. The effective load capacitance seen by a driver is derived for the decoupling method and distributed RLC transmission line models. The driver delay and rise time corresponding to the derived effective capacitance are used to derive the far-end voltage of a transmission line bus. The effects of process variation are taken into account in the characterization of the signaling circuitry and in the wire analysis. The overall delay variation of the bus due to device and wire process variation is then calculated. The model is verified by comparing it to HSPICE. We implement regular voltage mode, level-encoded dual-rail and 1-of-4 signaling circuitry and apply the derived model to analyze them. The implementation and analysis are done in 45 nm technology.
Place, publisher, year, edition, pages
2008. 228-234 p.
, International Conference on VLSI Design, Proceedings, ISSN 1063-9667
INTERCONNECT, CAPACITANCE, INDUCTANCE
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-74097DOI: 10.1109/VLSI.2008.73ISI: 000253939700043ISBN: 978-0-7695-3083-3OAI: oai:DiVA.org:kth-74097DiVA: diva2:489250
Joint Conference of the 21st International Conference on VLSI Design/7th International Conference on Embedded Systems. Hyderabad, INDIA. JAN 04-08, 2008
QC 201202032012-02-022012-02-022016-04-21Bibliographically approved