Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
System-level exploration of run-time clusterization for energy-efficient on-chip communication
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2009 (English)In: 2nd International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO42, 2009, 63-68 p.Conference paper, Published paper (Refereed)
Abstract [en]

System-level exploration of run-time power clusterization for energy-efficient on-chip communication is presented. Facilitated by multiple on-chip power-delivery-networks, areas of heavy or low traffics can be dynamically identified and adaptively supplied with new power schemes. This method is superior to design-time voltage island partitioning, in dealing with unpredictable spatial and temporal variations of communication traffics in large NoCs. Architectural design of the platform and online iterative configuration process are presented. The effectiveness of the proposed approach is demonstrated quantitatively on a NoC simulator with 65nm power models. With synthetic traffic traces characterizing various communication patterns, run-time power clusterization achieves considerable energy benefits compared to existing energy-efficient architectures (9% - 42% lower). The latency penalty is predictable and moderately bounded with minimal area overhead. The proposed architecture presents an ideal tradeoff, prioritizing energy efficiency, for massively parallel on-chip computing.

Place, publisher, year, edition, pages
2009. 63-68 p.
Keyword [en]
Network-on-Chip, energy-efficiency, on-chip communication, run-time clusterization, system-level design
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-74435DOI: 10.1145/1645213.1645228OAI: oai:DiVA.org:kth-74435DiVA: diva2:489639
Conference
2nd International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO42, New York, NY, 12 December, 2009
Note

QC 20120210

Available from: 2012-02-03 Created: 2012-02-03 Last updated: 2016-06-08Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full texthttp://doi.acm.org/10.1145/1645213.1645228

Search in DiVA

By author/editor
Guang, LiangNigussie, EthiopiaTenhunen, Hannu
By organisation
Electronic, Computer and Software Systems, ECS
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 6 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf