System-level exploration of run-time clusterization for energy-efficient on-chip communication
2009 (English)In: 2nd International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO42, 2009, 63-68 p.Conference paper (Refereed)
System-level exploration of run-time power clusterization for energy-efficient on-chip communication is presented. Facilitated by multiple on-chip power-delivery-networks, areas of heavy or low traffics can be dynamically identified and adaptively supplied with new power schemes. This method is superior to design-time voltage island partitioning, in dealing with unpredictable spatial and temporal variations of communication traffics in large NoCs. Architectural design of the platform and online iterative configuration process are presented. The effectiveness of the proposed approach is demonstrated quantitatively on a NoC simulator with 65nm power models. With synthetic traffic traces characterizing various communication patterns, run-time power clusterization achieves considerable energy benefits compared to existing energy-efficient architectures (9% - 42% lower). The latency penalty is predictable and moderately bounded with minimal area overhead. The proposed architecture presents an ideal tradeoff, prioritizing energy efficiency, for massively parallel on-chip computing.
Place, publisher, year, edition, pages
2009. 63-68 p.
Network-on-Chip, energy-efficiency, on-chip communication, run-time clusterization, system-level design
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-74435DOI: 10.1145/1645213.1645228OAI: oai:DiVA.org:kth-74435DiVA: diva2:489639
2nd International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO42, New York, NY, 12 December, 2009
QC 201202102012-02-032012-02-032016-06-08Bibliographically approved