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Run-time communication bypassing for energy-efficient, low-latency per-core DVFS on Network-on-Chip
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2010 (English)In: Proceedings - IEEE International SOC Conference, SOCC 2010, 2010, 481-486 p.Conference paper, Published paper (Refereed)
Abstract [en]

System-level exploration of a novel Network-on-Chip (NoC) architecture with run-time communication bypassing is presented. Fine-grained DVFS (Dynamic Voltage and Frequency Scaling) is an effective power reduction technique. We propose run-time reconfigurable interconnect on each inter-router channel to minimize the latency and energy overhead. When two routers are running on the same frequency, FIFO-channel is bypassed by direct interconnect. Distributed algorithm is designed for per-core DVFS. Proper power delivery and clocking scheme are integrated. Simulation shows significant energy and latency saving.

Place, publisher, year, edition, pages
2010. 481-486 p.
Keyword [en]
Electric power transmission; Embedded systems; Energy efficiency; Programmable logic controllers; Servers; VLSI circuits
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-74434DOI: 10.1109/SOCC.2010.5784674Scopus ID: 2-s2.0-79960708276OAI: oai:DiVA.org:kth-74434DiVA: diva2:489650
Conference
23rd IEEE International SOC Conference, SOCC 2010, Las Vegas, NV, 27-29 September, 2010
Note

QC 20120210

Available from: 2012-02-03 Created: 2012-02-03 Last updated: 2016-05-09Bibliographically approved

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  • apa
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  • Other locale
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Output format
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