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Analysis of Communication Delay Bounds for Network on Chips
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0003-0061-3475
2009 (English)In: PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009, 2009, 7-12 p.Conference paper, Published paper (Refereed)
Abstract [en]

In network-on-chip, computing worst-case delay bound for packet delivery is crucial for designing predictable systems but yet an intractable problem due to complicated resource contention scenarios. In this paper, we present an analysis technique to derive the communication delay bound for individual flows. Based on a network contention model, this technique, which is topology independent, employs the network calculus theory to first compute the equivalent service curve for individual flows and then calculate their packet delay bound. To exemplify our method, we also present the derivation of a closed-form formula to calculate the delay bound for all-to-one gather communication. Our experimental results demonstrate the theoretical bounds are correct and tight.

Place, publisher, year, edition, pages
2009. 7-12 p.
Series
Asia and South Pacific Design Automation Conference Proceedings
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-74576DOI: 10.1109/ASPDAC.2009.4796433ISI: 000265675400002Scopus ID: 2-s2.0-64549140251ISBN: 978-1-4244-2748-2 (print)OAI: oai:DiVA.org:kth-74576DiVA: diva2:489824
Conference
14th Asia and South Pacific Design Automation Conference. Yokohama, JAPAN. JAN 19-22, 2009
Note
QC 20120206Available from: 2012-02-03 Created: 2012-02-03 Last updated: 2012-02-06Bibliographically approved

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Lu, Zhonghai

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CiteExportLink to record
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Citation style
  • apa
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More styles
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  • nn-NO
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  • Other locale
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Output format
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