Analysis of Communication Delay Bounds for Network on Chips
2009 (English)In: PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009, 2009, 7-12 p.Conference paper (Refereed)
In network-on-chip, computing worst-case delay bound for packet delivery is crucial for designing predictable systems but yet an intractable problem due to complicated resource contention scenarios. In this paper, we present an analysis technique to derive the communication delay bound for individual flows. Based on a network contention model, this technique, which is topology independent, employs the network calculus theory to first compute the equivalent service curve for individual flows and then calculate their packet delay bound. To exemplify our method, we also present the derivation of a closed-form formula to calculate the delay bound for all-to-one gather communication. Our experimental results demonstrate the theoretical bounds are correct and tight.
Place, publisher, year, edition, pages
2009. 7-12 p.
, Asia and South Pacific Design Automation Conference Proceedings
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-74576DOI: 10.1109/ASPDAC.2009.4796433ISI: 000265675400002ScopusID: 2-s2.0-64549140251ISBN: 978-1-4244-2748-2OAI: oai:DiVA.org:kth-74576DiVA: diva2:489824
14th Asia and South Pacific Design Automation Conference. Yokohama, JAPAN. JAN 19-22, 2009
QC 201202062012-02-032012-02-032012-02-06Bibliographically approved