A Model of the Pantograph Arc Impedance for 50 Hz Catenary Voltage
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
The sliding contact between catenary and pantograph has to transfer a largeamount of current and power to the locomotive reliably. Sometimes detach-ment and attachment occur between the contact wire and the pantograph.This is related to the speed of the train as well as the lifting force of thepantograph. It leads to the creation of arcs whose visibility is also increasedby the current level and their probability of appearance by the presence ofa layer of ice (under harsh winter conditions) that could be formed on thebottom of the contact wire, which creates a separation between pantographand catenary.The ﬁrst goal of the work is to create a model of the arc impedance,based on previously done experimental investigations. The model aims tosimulate arc voltages (output) from experimental arc currents (input) whichdiﬀerentiate from each other by the RMS value, the voltage level, the powerfactor or the speed of the train. A strong link between the arc currentwaveform characteristics and the corresponding arc voltage has been broughtto light, leading to very good simulations: for each arc period, the voltage isstrongly related to the extreme value of the current over the same period.Once the model has been built and validated, it has been found that thesimulated arc voltages were quite similar to the experimental voltages, andthus that the main part of the information about the arc phenomenon iscontained in the arc current itself. The transient overvoltages as well as theaverage values are well modeled and approximated.Then, the modeled arc voltages have been studied in order to see howthe impedance model behaves when the arc currents have diﬀerent charac-teristics. Both thermal and dielectric reignitions (breakdowns) are correctlyrecreated, and the presence of a net DC voltage component (originating fromtransients and asymmetrically distorted waveforms) was also conﬁrmed forall the test runs.Finally, an electric circuit model is elaborated. Starting from a simplefrequency analysis, an RLC circuit has been simulated and the encouragingresults lead the way to a further study.
Place, publisher, year, edition, pages
EES Examensarbete / Master Thesis, XR-EE-ETK 2010:002EES Examensarbete / Master Thesis
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-74688OAI: oai:DiVA.org:kth-74688DiVA: diva2:489848