Applying Network Calculus for Worst-case Delay Bound Analysis in On-chip Networks
2009 (English)In: Proceedings of the DTIS'09 - 2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era / [ed] ElTahawy, H; Abadir, M; Jerraya, A; Salem, A, 2009, 113-118 p.Conference paper (Refereed)
In network-on-chip, computing worst-case delay bounds for packet delivery is crucial for designing predictable systems but yet an intractable problem due to complicated resource contention scenarios. In this paper, based on network calculus, we propose a technique for analyzing the communication delay bound for individual flows. The fundamental elements with the technique include three network calculus models that describe the traffic behaviors when flows are multiplexed, split, or controlled by feedback credits, respectively. Based on the basic models, we can compute the equivalent system service curve for individual flows and then calculate their packet delay bound.
Place, publisher, year, edition, pages
2009. 113-118 p.
Delay Bound, Network Contention, Network Calculus, Network-on-Chip, Performance Analysis
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-74574DOI: 10.1109/DTIS.2009.4938036ISI: 000269052000020ScopusID: 2-s2.0-67650398366ISBN: 978-1-4244-4320-8OAI: oai:DiVA.org:kth-74574DiVA: diva2:489856
4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era. Cairo, EGYPT. APR 06-07, 2009
QC 201507142012-02-032012-02-032015-07-14Bibliographically approved