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BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels
Turku Centre for Computer Science (TUCS) and University of Turku, Finland.
University of Turku, Finland.
University of Turku, Finland.
Turku Centre for Computer Science (TUCS) and University of Turku, Finland.
2010 (English)In: IEEE Annual Symposium on VLSI, ISVLSI 2010, 2010, 452-453 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, a 3D NoC architecture based on Bidirectional Bisynchronous Vertical Channels (BBVC) is proposed as a solution to mitigate area footprints of vertical interconnects. BBVCs, which can be dynamically self-configured to transmit flits in either direction, enable the system to benefit from a high-speed bidirectional channel instead of a pair of unidirectional channels for inter-layer communication. By exploiting the high-speed nature of the vertical links in 3D ICs, this substitution indicates better bandwidth utilization, lower area footprint, and improved routability at each layer. Our results reveal that the proposed architecture helps to achieve up to 47% savings in TSV area footprint at the 65nm technology node.

Place, publisher, year, edition, pages
2010. 452-453 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-74761DOI: 10.1109/ISVLSI.2010.21Scopus ID: 2-s2.0-77957928299ISBN: 978-076954076-4 (print)OAI: oai:DiVA.org:kth-74761DiVA: diva2:489960
Conference
IEEE Annual Symposium on VLSI, ISVLSI 2010. Lixouri, Kefalonia. 5 July 2010 - 7 July 2010
Note

QC 20120206

Available from: 2012-02-03 Created: 2012-02-03 Last updated: 2015-07-29Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
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