A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-layer Communication
2011 (English)In: 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011, 2011, 423-430 p.Conference paper (Refereed)
In this paper, an efficient architecture to optimize system performance, power consumption, and reliability of stacked mesh 3D NoC is proposed. Stacked mesh is a feasible architecture which takes advantage of the short inter-layer wiring delays, while suffering from inefficient intermediate buffers. To cope with this, an inter-layer communication mechanism is developed to enhance the buffer utilization, load balancing, and system fault-tolerance. The mechanism benefits from a congestion-aware and bus failure tolerant routing algorithm for vertical communication. To estimate the efficiency of the proposed architecture, the system has been simulated using uniform, hotspot 10, and Negative Exponential Distribution (NED) traffic patterns. In addition, a video conference encoder has been used as a real application for system analysis. Our extensive experiments show significant power and performance improvements compared to a typical stacked mesh 3D NoC.
Place, publisher, year, edition, pages
2011. 423-430 p.
3D ICs, 3D NoC-Bus Hybrid Architecture, Fault Tolerance, Routing Algorithm
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-74758DOI: 10.1109/PDP.2011.39ScopusID: 2-s2.0-79955028003OAI: oai:DiVA.org:kth-74758DiVA: diva2:489967
19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011. Ayia Napa. 9 February 2011 - 11 February 2011
QC 201202062012-02-032012-02-032015-07-29Bibliographically approved