Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels
2011 (English)In: 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011, Springer Berlin/Heidelberg, 2011, 278-287 p.Conference paper (Refereed)
3D NoC offers greater device integration, faster vertical interconnects and more power efficient inter-layer communication due to the beneficial attribute of short through silicon via (TSV) in 3D IC technologies. However, TSV pads used for bonding to a wafer layer, occupy significant chip area and result in routing congestions and expensive manufacturing process. This can lead to a significant reduction in 3D ICs' yield and higher power densities compared to 2D NoCs. In this paper, a power-efficient and low-cost inter-layer communication scheme is proposed as one way to mitigate these challenges. Instead of using a pair of unidirectional channels for inter-layer communication, utilizing a high-performance bidirectional channel enables a system to benefit from low-latency nature of the vertical interconnects and to remarkably reduce the number of TSVs. Additionally, we present a forecasting-based dynamic frequency scaling technique for reducing the power consumption of the inter-layer communication. Our extensive simulations demonstrate significant area and power improvements compared to a typical symmetric 3D NoC.
Place, publisher, year, edition, pages
Springer Berlin/Heidelberg, 2011. 278-287 p.
, Lecture Notes in Computer Science, ISSN 03029743 ; 6951
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-74757DOI: 10.1007/978-3-642-24154-3_28ISI: 000306294300028ScopusID: 2-s2.0-80053535054ISBN: 978-364224153-6OAI: oai:DiVA.org:kth-74757DiVA: diva2:489972
21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011. Madrid. 26 September 2011 - 29 September 2011
QC 201202062012-02-032012-02-032016-04-28Bibliographically approved