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Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels
University of Turku, Finland; Turku Centre for Computer Science (TUCS), Finland.
University of Turku, Finland; Turku Centre for Computer Science (TUCS), Finland.
University of Turku, Finland.
University of Turku, Finland.
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2011 (English)In: 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011, Springer Berlin/Heidelberg, 2011, 278-287 p.Conference paper, Published paper (Refereed)
Abstract [en]

3D NoC offers greater device integration, faster vertical interconnects and more power efficient inter-layer communication due to the beneficial attribute of short through silicon via (TSV) in 3D IC technologies. However, TSV pads used for bonding to a wafer layer, occupy significant chip area and result in routing congestions and expensive manufacturing process. This can lead to a significant reduction in 3D ICs' yield and higher power densities compared to 2D NoCs. In this paper, a power-efficient and low-cost inter-layer communication scheme is proposed as one way to mitigate these challenges. Instead of using a pair of unidirectional channels for inter-layer communication, utilizing a high-performance bidirectional channel enables a system to benefit from low-latency nature of the vertical interconnects and to remarkably reduce the number of TSVs. Additionally, we present a forecasting-based dynamic frequency scaling technique for reducing the power consumption of the inter-layer communication. Our extensive simulations demonstrate significant area and power improvements compared to a typical symmetric 3D NoC.

Place, publisher, year, edition, pages
Springer Berlin/Heidelberg, 2011. 278-287 p.
Series
Lecture Notes in Computer Science, ISSN 0302-9743 ; 6951
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-74757DOI: 10.1007/978-3-642-24154-3_28ISI: 000306294300028Scopus ID: 2-s2.0-80053535054ISBN: 9783642241536 (print)OAI: oai:DiVA.org:kth-74757DiVA: diva2:489972
Conference
21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011. Madrid. 26 September 2011 - 29 September 2011
Note

QC 20120206

Available from: 2012-02-03 Created: 2012-02-03 Last updated: 2017-03-29Bibliographically approved

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
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