Power-Efficient Inter-Layer Communication Architectures for 3D NoC
2011 (English)In: 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 2011, 355-356 p.Conference paper (Refereed)
In this work, an efficient hybridization architecture to optimize power consumption and system performance of Hybrid NoC-Bus 3D mesh is proposed. Hybrid NoC-Bus 3D mesh is a feasible architecture which takes advantage of the short interlayer wiring delays, while suffering from inefficient intermediate buffers. To address this issue, we propose a mechanism benefiting from a low-power congestion-aware routing algorithm for vertical communication. Our extensive simulations demonstrate significant power and performance improvements compared to a typical Hybrid NoC-Bus 3D architecture.
Place, publisher, year, edition, pages
2011. 355-356 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-74755DOI: 10.1109/ISVLSI.2011.12ISI: 000298386100074ScopusID: 2-s2.0-80052581511ISBN: 978-076954447-2OAI: oai:DiVA.org:kth-74755DiVA: diva2:489973
2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011. Chennai, India 4 July 2011 - 6 July 2011
QC 201507082012-02-032012-02-032015-07-29Bibliographically approved