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Power-Efficient Inter-Layer Communication Architectures for 3D NoC
Turku Centre for Computer Science (TUCS) and University of Turku.
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2011 (English)In: 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 2011, 355-356 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this work, an efficient hybridization architecture to optimize power consumption and system performance of Hybrid NoC-Bus 3D mesh is proposed. Hybrid NoC-Bus 3D mesh is a feasible architecture which takes advantage of the short interlayer wiring delays, while suffering from inefficient intermediate buffers. To address this issue, we propose a mechanism benefiting from a low-power congestion-aware routing algorithm for vertical communication. Our extensive simulations demonstrate significant power and performance improvements compared to a typical Hybrid NoC-Bus 3D architecture.

Place, publisher, year, edition, pages
2011. 355-356 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-74755DOI: 10.1109/ISVLSI.2011.12ISI: 000298386100074Scopus ID: 2-s2.0-80052581511ISBN: 978-076954447-2 (print)OAI: oai:DiVA.org:kth-74755DiVA: diva2:489973
Conference
2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011. Chennai, India 4 July 2011 - 6 July 2011
Note

QC 20150708

Available from: 2012-02-03 Created: 2012-02-03 Last updated: 2015-07-29Bibliographically approved

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Rahmani, Amir-MohammadTenhunen, Hannu
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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
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  • Other locale
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Output format
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