High Level Synthesis Framework for a Coarse Grain Reconfigurable Architecture
2010 (English)In: 28th Norchip Conference, NORCHIP 2010, 2010, 5669439- p.Conference paper (Refereed)
A High Level Synthesis Framework for mapping DSP algorithms on a Coarse Grain Reconfigurable Architecture is presented. Behavioral specification of the algorithm in C is specified with pragmas in comments and the tool generates configware after performing timing and synchronization synthesis. Pragmas identify SIMD type concurrency and sweep the architectural space with allocation and binding annotations to produce implementations from fully serial to fully parallel. This allows user to stay at algorithmic level and guide the HLS tool to search a restricted architectural space bounded by the pragmas thus making the synthesis process more efficient and predictable.
Place, publisher, year, edition, pages
2010. 5669439- p.
CGRA, High level language, High level synthesis, Symbolic assembler
IdentifiersURN: urn:nbn:se:kth:diva-74845DOI: 10.1109/NORCHIP.2010.5669439ScopusID: 2-s2.0-78751522042ISBN: 9781424489732OAI: oai:DiVA.org:kth-74845DiVA: diva2:490105
28th Norchip Conference, NORCHIP 2010; Tampere; 15 November 2010 through 16 November 2010
QC 201202232012-02-032012-02-032012-02-23Bibliographically approved