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Synchronizing distributed state machines in a coarse grain reconfigurable architecture
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
2011 (English)In: 2011 International Symposium on System on Chip, SoC 2011, 2011, 128-135 p.Conference paper (Refereed)
Abstract [en]

This work presents methodology for synchronizing distributed FSMs (Finite State Machines) which are generated while implementing different algorithms on a coarse grain reconfigurable architecture. These FSMs interact with each other while executing algorithms and they are dependent upon each other; thus they need to be synchronized with each other for performing correct execution. The algorithms presented in this paper makes appropriate use of different strategies available for synchronizing these FSMs. The tool hides all sorts of low level details from the Programmer. It lets the designer focus on the details of algorithm (at higher level of abstraction) and cycle by cycle timings are resolved automatically.

Place, publisher, year, edition, pages
2011. 128-135 p.
Keyword [en]
Distributed FSMs, System Level Synthesis
National Category
Embedded Systems
URN: urn:nbn:se:kth:diva-74847DOI: 10.1109/ISSOC.2011.6089690ScopusID: 2-s2.0-83755163725ISBN: 9781457706721OAI: diva2:490107
13th International Symposium on System-on-Chip, SoC 2011; Tampere; 31 October 2011 through 2 November 2011
QC 20120223Available from: 2012-02-03 Created: 2012-02-03 Last updated: 2012-02-23Bibliographically approved

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ReferencesLink to record
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