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Power Scalable Digital Baseband Architecture for IEEE 802.15.4
Microelectronics Lab., ECE Dept., Indian Institute of Science.ORCID iD: 0000-0001-7450-8681
2011 (English)In: 24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems, 2011, 30-35 p.Conference paper, Published paper (Refereed)
Abstract [en]

We propose a power scalable digital baseband for a low-IF receiver for IEEE 802.15.4-2006. The digital section's sampling frequency and bit width are used as knobs to reduce the power under favorable signal and interference scenarios, thus recovering the design margins introduced to handle worst case conditions. We propose tuning of these knobs based on measurements of Signal and the interference levels. We show that in a 0.13u CMOS technology, for an adaptive digital baseband section of the receiver designed to meet the 802.15.4 standard specification, power saving can be up to nearly 85% (0.49mW against 3.3mW) in favorable interference and signal conditions.

Place, publisher, year, edition, pages
2011. 30-35 p.
Series
Proceedings of the IEEE International Conference on VLSI Design, ISSN 1063-9667
Keyword [en]
IEEE 802.15.4; Low power; Power scalable receiver
National Category
Communication Systems
Identifiers
URN: urn:nbn:se:kth:diva-77390DOI: 10.1109/VLSID.2011.64Scopus ID: 2-s2.0-79952825402OAI: oai:DiVA.org:kth-77390DiVA: diva2:491536
Conference
24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems. Chennai. 2 January 2011 - 7 January 2011
Note

QC 20120208

Available from: 2012-02-06 Created: 2012-02-06 Last updated: 2017-03-27Bibliographically approved

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Dwivedi, Satyam

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  • apa
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  • nn-NB
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  • Other locale
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Output format
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