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Adaptative Techniques to Reduce Power in Digital Circuits
ECE Department, Indian Institute of Science/Bangalore.ORCID iD: 0000-0001-7450-8681
2011 (English)In: Journal of Low Power Electronics and Applications, ISSN 2079-9268, Vol. 1, no 2, 261-276 p.Article in journal (Refereed) Published
Abstract [en]

CMOS chips are engineered with sufficient performance margins to ensure that they meet the target performance under worst case operating conditions. Consequently, excess power is consumed for most cases when the operating conditions are more benign. This article will review a suite of dynamic power minimization techniques, which have been recently developed to reduce power consumption based on actual operating conditions. We will discuss commonly used techniques like Dynamic Power Switching (DPS), Dynamic Voltage and Frequency Scaling (DVS and DVFS) and Adaptive Voltage Scaling (AVS). Recent efforts to extend these to cover threshold voltage adaptation via Dynamic Voltage and Threshold Scaling (DVTS) will also be presented. Computation rate is also adapted to actual work load requirements via dynamically changing the hardware parallelism or by controlling the number of operations performed. These will be explained with some examples from the application domains of media and wireless signal processing.

Place, publisher, year, edition, pages
2011. Vol. 1, no 2, 261-276 p.
Keyword [en]
power adaptation; dynamic power switching; dynamic voltage scaling; dynamic voltage and frequency scaling; adaptive voltage scaling; dynamic voltage and threshold scaling; adaptive hardware parallelism; adaptive computation
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:kth:diva-77392DOI: 10.3390/jlpea1020261Scopus ID: 2-s2.0-84906810721OAI: oai:DiVA.org:kth-77392DiVA: diva2:491539
Note
QC 20120413Available from: 2012-02-06 Created: 2012-02-06 Last updated: 2012-04-13Bibliographically approved

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Dwivedi, Satyam

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