Non-planar devices for nanoscale CMOS
2007 (English)In: Nanoscaled Semiconductor-on-Insulator Structures and Devices, Springer Netherlands, 2007, 19-32 p.Conference paper (Refereed)
In this paper, various concepts of multi-gate transistors are discussed with regards to their technological feasibility and rnanufacturability. In addition, non-standard fabrication process modules for triplegate nanoscale MOSFETs and sub-10 nm nanowires are presented. Alternatives to costly extreme ultraviolet (EUV) lithography are proposed as well as a self-aligned nickel silicide module to reduce inherent parasitic access resistances.
Place, publisher, year, edition, pages
Springer Netherlands, 2007. 19-32 p.
, NATO Science for Peace and Security Series B - Physics and Biophysics, ISSN 1871-465X
SOI, FinFET, tri-gate, triple gate, nano-CMOS, nanowire
IdentifiersURN: urn:nbn:se:kth:diva-50571DOI: 10.1007/978-1-4020-6380-0_2ISI: 000248937200002ISBN: 978-1-4020-6378-7OAI: oai:DiVA.org:kth-50571DiVA: diva2:495257
NATO Advanced Research Workshop on Nanoscaled Semiconductor-on-Insulator Structures and Devices OCT 15-19, 2006 Big Yalta, UKRAINE
QC 201202222012-02-082011-12-062012-02-22Bibliographically approved