Examination of Delay and Signal Integrity Metrics in Through Silicon Vias
2009 (English)In: DATE'09 Friday Workshops - 3D Integration - Technology, Architecture, Design, Automation, and Test, Electronic Workshop Digest, Palais des Congrès Acropolis – Nice, France, Friday April 24, 2009, Nice, France, 2009, 260-264 p.Conference paper (Refereed)
This article discusses results from simulations of signaling in Through Silicon Vias (TSVs) with an emphasis on latency and signal integrity effects. Data from field solver simulations is used for TSV parasitics and employed in SPICE simulations. A reduced order electrical circuit is proposed for lone TSVs as well as bundled structures and switch-factor based delay models are derived to calculate rise times in a 3x3 bundle. Furthermore Signal Integrity (SI) issues in coupled TSVs are briefly discussed.
Place, publisher, year, edition, pages
Nice, France, 2009. 260-264 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-79240OAI: oai:DiVA.org:kth-79240DiVA: diva2:495281
DATE'09 Friday Workshops - 3D Integration - Technology, Architecture, Design, Automation, and Test, Nice, France, April 24, 2009
QC 201202092012-02-082012-02-082012-02-10Bibliographically approved