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Examination of Delay and Signal Integrity Metrics in Through Silicon Vias
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2009 (English)In: DATE'09 Friday Workshops - 3D Integration - Technology, Architecture, Design, Automation, and Test, Electronic Workshop Digest, Palais des Congrès Acropolis – Nice, France, Friday April 24, 2009, Nice, France, 2009, 260-264 p.Conference paper, Published paper (Refereed)
Abstract [en]

This article discusses results from simulations of signaling in Through Silicon Vias (TSVs) with an emphasis on latency and signal integrity effects. Data from field solver simulations is used for TSV parasitics and employed in SPICE simulations. A reduced order electrical circuit is proposed for lone TSVs as well as bundled structures and switch-factor based delay models are derived to calculate rise times in a 3x3 bundle. Furthermore Signal Integrity (SI) issues in coupled TSVs are briefly discussed.

Place, publisher, year, edition, pages
Nice, France, 2009. 260-264 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-79240OAI: oai:DiVA.org:kth-79240DiVA: diva2:495281
Conference
DATE'09 Friday Workshops - 3D Integration - Technology, Architecture, Design, Automation, and Test, Nice, France, April 24, 2009
Projects
EU-FP7 ELITE-215030
Note
QC 20120209Available from: 2012-02-08 Created: 2012-02-08 Last updated: 2012-02-10Bibliographically approved

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http://www.date-conference.com/files/file/09-workshops/date09-3dws-digestv2-090504.pdf

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Pamunuwa, DineshTenhunen, Hannu
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CiteExportLink to record
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  • Other locale
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