Suspended silicon-on-insulator nanowires for the fabrication of quadruple gate mosfets
2007 (English)In: Nanoscaled Semiconductor-on-Insulator Structures and Devices, 2007, 89-94 p.Conference paper (Refereed)
Scaling of MOSFET physical dimensions is approaching the OF nanoscale regime, which causes increase of short-channel effects such that the electrical performance of classical MOSFET structure is becoming seriously degraded. The limits of silicon scaling have been the major challenge for technologists for the past years. With the 90 nm generation in production and despite many roadblocks, the latest International Roadmap for Semiconductors 2005 expects that CMOS can be scaled down to 16 nm, by introducing new transistor architectures and materials. In this paper, we propose fabrication of a non-classical device architecture namely the "Quadruple-Gate MOSFET" which is based on definition of narrow, suspended silicon fins defined by electron-beam lithography into the top-silicon film of a Silicon-on-Insulator (SOI) wafer.
Place, publisher, year, edition, pages
2007. 89-94 p.
, NATO Science for Peace and Security Series B - Physics and Biophysics, ISSN 1871-465X
electron-beam lithography, quadruple-gate, silicon-on-insulator
IdentifiersURN: urn:nbn:se:kth:diva-50562DOI: 10.1007/978-1-4020-6380-0_6ISI: 000248937200006ISBN: 978-1-4020-6378-7OAI: oai:DiVA.org:kth-50562DiVA: diva2:495289
NATO Advanced Research Workshop on Nanoscaled Semiconductor-on-Insulator Structures and Devices. Big Yalta, UKRAINE. OCT 15-19, 2006
QC 201203022012-02-082011-12-062012-03-02Bibliographically approved