On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits
2010 (English)In: Design, Automation and Test in Europe Conference and Exhibition, DATE 2010, 2010, 1325-1328 p.Conference paper (Refereed)
This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in Spice simulations to investigate the effect of each parasitic component on performance metrics such as delay and crosstalk and identify a reduced-order electrical model that captures all relevant effects. We show that in dense TSV structures voltage-mode (VM) signalling does not lend itself to achieving high data-rates, and that current-mode (CM) signalling is more effective for high throughput signalling as well as jitter reduction. Data rates, energy consumption and coupled noise for the different signalling modes are extracted.
Place, publisher, year, edition, pages
2010. 1325-1328 p.
3D integrated circuits;Spice simulations;current-mode signalling;jitter reduction;reduced-order electrical model;signal integrity;through-silicon via interconnects;voltage-mode signalling;SPICE;crosstalk;integrated circuit interconnections;
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-79285ScopusID: 2-s2.0-77953116301ISBN: 978-1-4244-7054-9OAI: oai:DiVA.org:kth-79285DiVA: diva2:495291
Design, Automation and Test in Europe Conference and Exhibition, DATE 2010. Dresden. 8 March 2010 - 12 March 2010
QC 201202092012-02-082012-02-082012-02-12Bibliographically approved