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Modeling the Efficiency of Stacked Silicon Systems: Computational, Thermal and Electrical Performance
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2011 (English)Conference paper (Refereed)
Abstract [en]

Technological advances in processor design have typically reliedon scaling feature size and frequency. Recently however, many new design choiceshave emerged partly due to the slowing of scaling:– Many-core architectures arebeginning to replace single-core ICs to circumvent 2-D bottlenecks, The number ofI/Os are on the rise, so the cost of off-chip transactions is becoming heftier. Moreover,3-D Integration may provide further performance benefits without investment in lowertechnology nodes. Understanding these trade-offs can provide guidelines to optimizethe architecture of future systems under performance, thermal and cost constraints.We have constructed a model and tool that assesses computational efficiency underthese criteria.

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Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-79324OAI: diva2:495307
Special Interest Workshop on 3D Integration - Applications, Technology, Architecture, Design, Automation, and Test, Design Automation and Test in Europe (DATE). Grenoble, France. 14-18 March 2011
Poster. QC 20120412 Available from: 2012-02-08 Created: 2012-02-08 Last updated: 2012-04-12Bibliographically approved

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Jantsch, AxelPamunuwa, Dinesh
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