Modeling the Efficiency of Stacked Silicon Systems: Computational, Thermal and Electrical Performance
2011 (English)Conference paper (Refereed)
Technological advances in processor design have typically reliedon scaling feature size and frequency. Recently however, many new design choiceshave emerged partly due to the slowing of scaling:– Many-core architectures arebeginning to replace single-core ICs to circumvent 2-D bottlenecks, The number ofI/Os are on the rise, so the cost of off-chip transactions is becoming heftier. Moreover,3-D Integration may provide further performance benefits without investment in lowertechnology nodes. Understanding these trade-offs can provide guidelines to optimizethe architecture of future systems under performance, thermal and cost constraints.We have constructed a model and tool that assesses computational efficiency underthese criteria.
Place, publisher, year, edition, pages
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-79324OAI: oai:DiVA.org:kth-79324DiVA: diva2:495307
Special Interest Workshop on 3D Integration - Applications, Technology, Architecture, Design, Automation, and Test, Design Automation and Test in Europe (DATE). Grenoble, France. 14-18 March 2011
Poster. QC 20120412 2012-02-082012-02-082012-04-12Bibliographically approved