Fabrication of wire-MOSFETs on silicon-on-insulator substrate
2002 (English)In: Microelectronic Engineering, ISSN 0167-9317, Vol. 61-2, 613-618 p.Article in journal (Refereed) Published
This paper describes the simulation and fabrication of N-type wire-MOSFETs with a multigate structure fabricated on silicon-on-insulator (SOI) material. Both simulations as well as experiments show that short channel effects (SCE) can be reduced by decreasing the channel width of the transistors below 100 nm. The triple-sided gate generates principally higher potential barriers in the channel, suppressing punch through effects significantly. (C) 2002 Elsevier Science B.V. All rights reserved.
Place, publisher, year, edition, pages
2002. Vol. 61-2, 613-618 p.
wire MOSFET, silicon-on-insulator (SOI), double gate, fully depleted, triple-sided gate structure
IdentifiersURN: urn:nbn:se:kth:diva-50545DOI: 10.1016/S0167-9317(02)00465-3ISI: 000176594700084OAI: oai:DiVA.org:kth-50545DiVA: diva2:495337
NR 201408052012-02-082011-12-062012-02-08Bibliographically approved