Tungsten work function engineering for dual metal gate nano-CMOS
2005 (English)In: Journal of materials science. Materials in electronics, ISSN 0957-4522, E-ISSN 1573-482X, Vol. 16, no 7, 433-436 p.Article in journal (Refereed) Published
A buffer layer technology for work function engineering of tungsten for dual metal gate Nano-CMOS is investigated. For the first time, tungsten is used as a p-type gate material using 1 nm of sputtered Aluminum Nitride (AlNx) as a buffer layer on silicon dioxide (SiO2) gate dielectric. A tungsten work function of 5.12 eV is realized using this technology in contrast to a mid-gap value of 4.6 eV without a buffer layer. Device characteristics of a p-MOSFET on silicon-on-insulator (SOI) substrate fabricated with this technology are presented.
Place, publisher, year, edition, pages
2005. Vol. 16, no 7, 433-436 p.
Aluminum nitride; CMOS integrated circuits; Composition effects; Dielectric devices; Energy gap; MOSFET devices; Nanotechnology; Silica; Silicon on insulator technology
IdentifiersURN: urn:nbn:se:kth:diva-50538DOI: 10.1007/s10854-005-2310-8ISI: 000231502200010OAI: oai:DiVA.org:kth-50538DiVA: diva2:495365
QC 201202172012-02-082011-12-062012-02-17Bibliographically approved