Electrical characterization of 12 nm EJ-MOSFETs on SOI substrates
2004 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 48, no 5, 739-745 p.Article in journal (Refereed) Published
A dual gate metal oxide semiconductor field effect transistor (MOSFET) with electrically variable shallow junctions (EJ-MOSFET) has been fabricated on silicon on insulator (SOI) substrates. This kind of transistor allows testing the limits of scalability at relaxed process requirements. Transistor gate lengths down to 12 run have been structured by electron beam lithography (EBL) and specific etching processes. The coupling of the upper gate to the inner transistor is carefully investigated.
Place, publisher, year, edition, pages
2004. Vol. 48, no 5, 739-745 p.
EJ-MOSFET, 12 nm gate length, shallow junction, SOI, HSQ, electron beam lithography
IdentifiersURN: urn:nbn:se:kth:diva-50537DOI: 10.1016/j.sse.2003.09.037ISI: 000220123300014OAI: oai:DiVA.org:kth-50537DiVA: diva2:495366
QC 201203052012-02-082011-12-062012-03-05Bibliographically approved