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Scalable gate first process for silicon on insulator metal oxide semiconductor field effect transistors with epitaxial high-k dielectrics
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2006 (English)In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 24, no 2, 710-714 p.Article in journal (Refereed) Published
Abstract [en]

A "gate first" silicon on insulator (SOI) complementary metal oxide semiconductor process technology for direct evaluation of epitaxial gate dielectrics is described, where the gate stack is fabricated prior to any lithography or etching step. This sequence provides perfect silicon surfaces required for epitaxial growth. The inverted process flow with silicon dioxide (SiO2)/polysilicon gate stacks is demonstrated for gate lengths from 10 mu m down to 40 nm on a fully depleted 25 nm thin SOI film. The interface qualities at the front and back gates are investigated and compared to conventionally processed SOI devices. Furthermore, the subthreshold behavior is studied and the scalability of the gate first approach is proven by fully functional sub-100 nm transistors. Finally, a fully functional gate first metal oxide semiconductor field effect transistor with the epitaxial high-k gate dielectric gadolinium oxide (Gd2O3) and titanium nitride (TiN) gate electrode is presented.

Place, publisher, year, edition, pages
2006. Vol. 24, no 2, 710-714 p.
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Nano Technology
Identifiers
URN: urn:nbn:se:kth:diva-50527DOI: 10.1116/1.2180256ISI: 000237172000038OAI: oai:DiVA.org:kth-50527DiVA: diva2:495381
Note
QC 20120229Available from: 2012-02-08 Created: 2011-12-06 Last updated: 2017-12-07Bibliographically approved

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Lemme, Max C.
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