Nanoscale TiN metal gate technology for CMOS integration
2006 (English)In: Microelectronic Engineering, ISSN 0167-9317, Vol. 83, no 4-9, 1551-1554 p.Article in journal (Refereed) Published
A TiN metal gate technology including essential natiostructuring process steps is investigated. Complex interdependencies of material deposition, nanolithography, nanoscale etching and post fabrication annealing are taken into account. First, a reactive sputter process has been optimized for plasma damage and stoichiometry. Then, a two step etch process that yields both anisotropy and selectivity has been identified. Finally, MOS-capacitors with TiN/SiO2 gate stacks fabricated with this technology have been exposed to rapid thermal annealing steps. TiN/SiO2 interfaces are chemically stable up to 800 degrees C and yield excellent CV and IV characteristics.
Place, publisher, year, edition, pages
2006. Vol. 83, no 4-9, 1551-1554 p.
nanoelectronics, metal gate, RIE etching, nanostructuring, TiN
IdentifiersURN: urn:nbn:se:kth:diva-50524DOI: 10.1016/j.mee.2006.01.161ISI: 000237581900225OAI: oai:DiVA.org:kth-50524DiVA: diva2:495383
QC 201202222012-02-082011-12-062012-02-22Bibliographically approved