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Influence of channel width on n- and p-type nano-wire-MOSFETs on silicon on insulator substrate
AMO GmbH, AMICA, Aachen, Germany.
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2003 (English)In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 67-8, 810-817 p.Article in journal (Refereed) Published
Abstract [en]

The fabrication and characterization of nanoscale n- and p-type multi-wire metal-oxide semiconductor field effect transistors (MOSFETs) with a triple gate structure on silicon-on-insulator material (SOI) is described in this paper. Experimental results are compared to simulation with special emphasis on the influence of channel width on the subthreshold behavior. Experiment and simulation show that the threshold voltage depends strongly on the wire width at dimensions below 100 urn. It is further shown that the transition from partial to full channel depletion is dependent on channel geometry. Finally, an increased on-current per chip area is demonstrated for triple-gate SOI MOSFETs compared to planar SOI devices. (C) 2003 Elsevier Science B.V. All rights reserved.

Place, publisher, year, edition, pages
2003. Vol. 67-8, 810-817 p.
Keyword [en]
double gate, FinFET, multi gate, SOI, triple gate
National Category
Nano Technology
Identifiers
URN: urn:nbn:se:kth:diva-50521DOI: 10.1016/S0167-9317(03)00191-6ISI: 000183842100112OAI: oai:DiVA.org:kth-50521DiVA: diva2:495386
Note
NR 20140805Available from: 2012-02-08 Created: 2011-12-06 Last updated: 2017-12-07Bibliographically approved

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