Highly selective HBr etch process for fabrication of Triple-Gate nano-scale SOI-MOSFETs
2004 (English)In: Microelectronic Engineering, ISSN 0167-9317, Vol. 73-74, no SI, 346-350 p.Article in journal (Refereed) Published
New three-dimensional device concepts are considered necessary for the ultimate scaling of the gate length of metal-oxide-semiconductor field effect transistors (MOSFETs). Both Triple-Gate field effect transistors and FinFETs require a gate etch process with excellent selectivity over the gate oxide material. In this work, a highly selective, anisotropic gate etch process using HBr and O-2 as the reactive gases in an inductively coupled plasma reactive ion etch tool is described. Polysilicon thickness measurements have been taken to calculate etch rate and uniformity. Polysilicon wafers for each experimental condition were given different overetch times and SiO2 losses were plotted against time, with the gradient yielding the SiO2 etch rate. The optimized etch process yields excellent results for nanoscale polysilicon gates.
Place, publisher, year, edition, pages
2004. Vol. 73-74, no SI, 346-350 p.
Triple-Gate MOSFET, SOI, HBr, FinFET
IdentifiersURN: urn:nbn:se:kth:diva-50515DOI: 10.1016/j.mee.2004.02.065ISI: 000222145400061OAI: oai:DiVA.org:kth-50515DiVA: diva2:495392
QC 201202222012-02-082011-12-062012-02-22Bibliographically approved