Case study of interconnect analysis for standing wave oscillator design
2005 (English)In: 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, 456-459 p.Conference paper (Refereed)
As a result of continuous downscaling CMOS technology, on-chip interconnects play critical role in highspeed circuits design. In this paper, geometry based accurate circuit model of interconnect is extracted for high-speed circuits design and analysis. This is demonstrated through a 10GHz standing wave oscillator (SWO) for global clock distribution. The results show that the skew of the clock is well controlled (about 1ps) while the clock frequency variation is about 20% because power/ground return paths exist in different metal layers. Hence, for high-speed circuits, the parameters of interconnect should be predictable according to its geometry in order to avoid design iterations and speed time-to-market. Meanwhile, robust circuit architectures should be adopted for tolerating the parameters variation of interconnects.
Place, publisher, year, edition, pages
2005. 456-459 p.
, IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
10 GHz; CMOS SWO; clock frequency variation; clock skew; geometry based interconnect circuit model; global clock distribution oscillator; high-speed circuits; interconnect circuit model; metal layer power/ground return paths; on-chip interconnect analysis; parameter variation tolerance; standing wave oscillator; CMOS integrated circuits; MMIC oscillators; integrated circuit interconnections; integrated circuit modelling;
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-79927DOI: 10.1109/ISCAS.2005.1464623ISI: 000232002400115ScopusID: 2-s2.0-51849105602OAI: oai:DiVA.org:kth-79927DiVA: diva2:496269
IEEE International Symposium on Circuits and Systems (ISCAS). Kobe, JAPAN. MAY 23-26, 2005
QC 201202272012-02-092012-02-092012-02-27Bibliographically approved