Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Performance and cost trade-offs for SoC, SoP and 3-D integration
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2007 (English)Conference paper, Published paper (Other academic)
Place, publisher, year, edition, pages
2007.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-80394OAI: oai:DiVA.org:kth-80394DiVA: diva2:496273
Conference
IEEE Solid-State Circuits Conference (ISSCC), Forum on Design of 3D-Chipstacks. San Francisco, CA, USA. 11-15 Feb. 2007
Note
QC 20120522Available from: 2012-02-09 Created: 2012-02-09 Last updated: 2012-05-22Bibliographically approved

Open Access in DiVA

No full text

Search in DiVA

By author/editor
Tenhunen, HannyZheng, Li-Rong
By organisation
Electronic, Computer and Software Systems, ECS
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar

urn-nbn

Altmetric score

urn-nbn
Total: 13 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf