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Within-die process variations: How accurately can they be statistically modeled?
Brown University. (Electrical Engineering)
Brown University. (Electrical Engineering)
2008 (English)Conference paper, Published paper (Refereed)
Abstract [en]

Within-die process variations arise during integrated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviate the performance of ICs from their designers’ original intent. These deviations reduce the parametric yield and revenues from integrated circuit fabrication. In this paper we provide a complete treatment to the subject of within-die variations. We propose a scan-chain based system, vMeter, to extract within-die variations in an automated fashion. We implement our system in a sample of 90nm chips, and collect the within-die variations data. Then we propose a number of novel statistical analysis techniques that accurately model the within-die variation trends and capture the spatial correlations. We propose the use of maximum-likelihood techniques to find the required parameters to fit the model to the data. The accuracy of our models is statistically verified through residua lanalysis and variograms. Using our successful modeling technique, we propose a procedure to generate synthetic within-dievariation patterns that mimic, or imitate, real silicon data.

Place, publisher, year, edition, pages
2008.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-81928OAI: oai:DiVA.org:kth-81928DiVA: diva2:497769
Conference
13th Asia and South Pacific Design Automation Conference
Note
QC 20120214Available from: 2012-02-11 Created: 2012-02-11 Last updated: 2012-02-14Bibliographically approved

Open Access in DiVA

No full text

Other links

http://scale.engin.brown.edu/pubs/aspdac08.pdf

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Hult, Henrik

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