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A High-Resolution Time-to-Digital Converter Based on Parallel Delay Elements
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
2012 (English)In: ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems, IEEE Solid-State Circuits Society, 2012, 3158-3161 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a flash-type Time to Digital Converter (TDC) based on parallel delay elements in 65-nm CMOS process technology. By using parallel delay elements the conversion resolution of the TDC becomes equal to the difference of delay elements rather than the delay time of each element. A Sensed Amplifier Flip Flop (SAFF) ensures narrow sampling window. Operating at 1.2-V supply, this TDC shows 3ps resolution with 0.5LSB of INL and 0.33LSB of DNL respectively and consumes average power 442 mu W.

Place, publisher, year, edition, pages
IEEE Solid-State Circuits Society, 2012. 3158-3161 p.
Series
IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
Keyword [en]
Average power, CMOS process technology, Delay elements, Delay Time, High resolution, Sampling windows, Time to digital converters
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-83070DOI: 10.1109/ISCAS.2012.6271992ISI: 000316903703089Scopus ID: 2-s2.0-84866594086ISBN: 978-1-4673-0218-0 (print)OAI: oai:DiVA.org:kth-83070DiVA: diva2:498670
Conference
2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, 20 May 2012 through 23 May 2012
Funder
ICT - The Next Generation
Note

QC 20130111

Available from: 2012-02-12 Created: 2012-02-12 Last updated: 2013-05-27Bibliographically approved

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