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Utilizing NoC Switches as BIST Structures in 2D-Mesh Network-on-Chips
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0002-8072-1742
2006 (English)In: Proceedings of NoC Workshop, DATE 2006, 2006Conference paper, Published paper (Refereed)
Abstract [en]

¨This poster proposes a test methodology and presents amethod for carrying out an automatic go/no-go BIST operationat start up of a 2D-mesh NoC Network. It executes infunctional mode at full clock speed. Only minor area penaltyis introduced in the NoC-network itself; the BIST is placed inthe Network-Interface inside the computational resources.

Place, publisher, year, edition, pages
2006.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-84457OAI: oai:DiVA.org:kth-84457DiVA: diva2:499341
Conference
DATE-2006. Munich, Germany. 6-10 March 2006
Note
QC 20120528Available from: 2012-02-13 Created: 2012-02-13 Last updated: 2012-05-28Bibliographically approved

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Öberg, Johnny

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