A performance and energy exploration of dictionary code compression architectures
2011 (English)In: 2011 International Green Computing Conference and Workshops (IGCC), IEEE conference proceedings, 2011, 1-8 p.Conference paper (Refereed)
We have made a performance and energy exploration of a previously proposed dictionary code compression mechanism where frequently executed individual instructions and/or sequences are replaced in memory with short code words. Our simulated design shows a dramatically reduced instruction memory access frequency leading to a performance improvement for small instruction cache sizes and to significantly reduced energy consumption in the instruction fetch path. We have evaluated the performance and energy implications of three architectural parameters: branch prediction accuracy, instruction cache size and organization. To asses the complexity of the design we have implemented the critical stages in VHDL.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2011. 1-8 p.
CPU architecture, Code compression, low energy architecture
IdentifiersURN: urn:nbn:se:kth:diva-89621DOI: 10.1109/IGCC.2011.6008584ScopusID: 2-s2.0-80053208021ISBN: 978-1-4577-1222-7OAI: oai:DiVA.org:kth-89621DiVA: diva2:503170
IGCC'2011, Orlando, Florida, USA, July 25-28, 2011
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QC 201202152012-02-152012-02-152012-02-15Bibliographically approved