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Architecture-aware Task-scheduling: A thermal approach
KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture, Software and Computer Systems, SCS. (Kista Multicore Center)
KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture, Software and Computer Systems, SCS. (Kista Multicore Center)ORCID iD: 0000-0002-9637-2065
2011 (English)In:, 2011Conference paper (Refereed)
Abstract [en]

Current task-centric many-core schedulers share a “naive” view of processor architecture; a view that does not care about its thermal, architectural or power consuming properties. Future processor will be more heterogeneous than what we see today, and following Moore’s law of transistor doubling, we foresee an increase in power consumption and thus temperature.

Thermal stress can induce errors in processors, and so a common way to counter this is by slowing the processor down; something task-centric schedulers should strive to avoid. The Thermal-Task-Interleaving scheduling algorithm proposed in this paper takes both the application temperature behavior and architecture into account when making decisions. We show that for a mixed workload, our scheduler outperforms some of the standard, architecture-unaware scheduling solutions existing today.

Place, publisher, year, edition, pages
Keyword [en]
OpenMP, Tasks, Power, Thermal, Temperature, Scheduling, Many-core, Tilera
National Category
Computer Engineering
URN: urn:nbn:se:kth:diva-89634OAI: diva2:503186
QC 20120215Available from: 2012-02-15 Created: 2012-02-15 Last updated: 2015-10-16Bibliographically approved
In thesis
1. Performance-driven exploration using Task-based Parallel Programming Frameworks
Open this publication in new window or tab >>Performance-driven exploration using Task-based Parallel Programming Frameworks
2013 (English)Licentiate thesis, comprehensive summary (Other academic)
Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2013. 39 p.
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 13:08
National Category
Computer Systems
urn:nbn:se:kth:diva-122569 (URN)978-91-7501-718-1 (ISBN)
2013-05-28, Sal D, KTH Kista Forum, Isafjordsagatan 39, Kista, 13:00 (English)

QC 20130530

Available from: 2013-05-30 Created: 2013-05-23 Last updated: 2013-06-25Bibliographically approved
2. Improving Performance and Quality-of-Service through the Task-Parallel Model​: Optimizations and Future Directions for OpenMP
Open this publication in new window or tab >>Improving Performance and Quality-of-Service through the Task-Parallel Model​: Optimizations and Future Directions for OpenMP
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

With the failure of Dennard's scaling, which stated that shrinking transistors will be more power-efficient, computer hardware has today become very divergent. Initially the change only concerned the number of processor on a chip (multicores), but has today further escalated into complex heterogeneous system with non-intuitive properties -- properties that can improve performance and power consumption but also strain the programmer expected to develop on them.

Answering these challenges is the OpenMP task-parallel model -- a programming model that simplifies writing parallel software. Our focus in the thesis has been to explore performance and quality-of-service directions of the OpenMP task-parallel model, particularly by taking architectural features into account.

The first question tackled is: what capabilities does existing state of the art runtime-systems have and how do they perform? We empirically evaluated the performance of several modern task-parallel runtime-systems. Performance and power-consumption was measured through the use of benchmarks and we show that the two primary causes for bottlenecks in modern runtime-systems lies in either the task management overheads or how tasks are being distributed across processors.

Next, we consider quality-of-service improvements in task-parallel runtime-systems. Striving to improve execution performance, current state of the art runtime-systems seldom take dynamic architectural features such as temperature into account when deciding how work should be distributed across the processors, which can lead to overheating. We developed and evaluated two strategies for thermal-awareness in task-parallel runtime-systems. The first improves performance when the computer system is constrained by temperature while the second strategy strives to reduce temperature while meeting soft real-time objectives.

We end the thesis by focusing on performance. Here we introduce our original contribution called BLYSK -- a prototype OpenMP framework created exclusively for performance research.

We found that overheads in current runtime-systems can be expensive, which often lead to performance degradation. We introduce a novel way of preserving task-graphs throughout application runs: task-graphs are recorded, identified and optimized the first time an OpenMP application is executed and are later re-used in following executions, removing unnecessary overheads. Our proposed solution can nearly double the performance compared with other state of the art runtime-systems.

Performance can also be improved through heterogeneity. Today, manufacturers are placing processors with different capabilities on the same chip. Because they are different, their power-consuming characteristics and performance differ. Heterogeneity adds another dimension to the multiprocessing problem: how should work be distributed across the heterogeneous processors?We evaluated the performance of existing, homogeneous scheduling algorithms and found them to be an ill-match for heterogeneous systems. We proposed a novel scheduling algorithm that dynamically adjusts itself to the heterogeneous system in order to improve performance.

The thesis ends with a high-level synthesis approach to improve performance in task-parallel applications. Rather than limiting ourselves to off-the-shelf processors -- which often contains a large amount of unused logic -- our approach is to automatically generate the processors ourselves. Our method allows us to generate application-specific hardware from the OpenMP task-parallel source code. Evaluated using FPGAs, the performance of our System-on-Chips outperformed other soft-cores such as the NiosII processor and were also comparable in performance with modern state of the art processors such as the Xeon PHI and the AMD Opteron.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. 64 p.
, TRITA-ICT, 2015:13
Task Parallel, OpenMP, Scheduling, OmpSs, multicore, manycore
National Category
Communication Systems
Research subject
Computer Science
urn:nbn:se:kth:diva-175539 (URN)978-91-7595-711-1 (ISBN)
Public defence
2015-11-10, Sal A, KTH Kista, Electrum Kistagången 16, Kista, 10:00 (English)

QC 20151016

Available from: 2015-10-16 Created: 2015-10-16 Last updated: 2015-10-16Bibliographically approved

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