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Exploring ASIC Design Space at System Level with a Neural Network Estimator
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Electronic Systems Design.ORCID iD: 0000-0002-8072-1742
KTH, Superseded Departments, Electronic Systems Design.ORCID iD: 0000-0003-0565-9376
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1994 (English)In: Proc. of IEEE ASIC-conference, 1994, 1994Conference paper, Published paper (Refereed)
Abstract [en]

Estimators are critical tools in doing architectural level exploration of the design space. We present a novel approach to estimation based on the multilayer perceptron which builds the estimation function during the learning process and thus allows to describe arbitrary complex functions. We also describe how the control data flow graph is encoded for the neural network input and we present results of the first experiments made with realistic design examples.

Place, publisher, year, edition, pages
1994.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-89937OAI: oai:DiVA.org:kth-89937DiVA: diva2:503980
Conference
7th Annual IEEE international ASIC-conference, ASIC'94
Note

QC 20121121

Available from: 2012-02-17 Created: 2012-02-17 Last updated: 2012-11-21Bibliographically approved

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Öberg, JohnnyHemani, Ahmed

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Ellervee, PeeterJantsch, AxelÖberg, JohnnyHemani, AhmedTenhunen, Hannu
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