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Layered Spiral Algorithm for memory-aware mapping and scheduling on Network-on-Chip
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0002-4157-4487
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
Department of Electronics and Computer Engineering, School of Engineering, Jönköping University.
2010 (English)In: 28th Norchip Conference, NORCHIP 2010, 2010Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, Layered Spiral Algorithm (LSA) is proposed for memory-aware application mapping and scheduling onto Network-on-Chip (NoC) based Multi-Processor System-on-Chip (MPSoC). The energy consumption is optimized while keeping high task level parallelism. The experimental evaluation indicates that if memory-awareness is not considered during mapping and scheduling, memory overflows may occur. The underlying problem is also modeled as a Mixed Integer Linear Programming (MILP) problem and solved using an efficient branch-and-bound algorithm to compare optimal solutions with results achieved by LSA. Comparing to MILP solutions, the LSA results demonstrate only about 20% and 12% increase of total communication cost in case of a small and middle size synthetic problem, respectively, while it is order of magnitude faster than the MILP solutions. Therefore, the LSA can find acceptable total communication cost with a low run-time complexity, enabling quick exploration of large design spaces, which is infeasible for exhaustive search.

Place, publisher, year, edition, pages
2010.
Keyword [en]
branch-and-bound algorithm;energy consumption;exhaustive search;layered spiral algorithm;memory-aware application mapping;memory-aware scheduling;mixed integer linear programming problem;multiprocessor system-on-chip;network-on-chip;energy consumption;integer programming;linear programming;multiprocessing systems;network-on-chip;processor scheduling;tree searching;
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-90722DOI: 10.1109/NORCHIP.2010.5669442Scopus ID: 2-s2.0-78751521501OAI: oai:DiVA.org:kth-90722DiVA: diva2:506185
Conference
28th Norchip Conference, NORCHIP 2010. Tampere. 15 November 2010 - 16 November 2010
Note
QC 20120312Available from: 2012-02-28 Created: 2012-02-28 Last updated: 2012-03-12Bibliographically approved

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Li, ShuoHemani, Ahmed

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  • apa
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Output format
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