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Optimal Selection of Function Implementation in a Hierarchical Configware Synthesis Method for a Coarse Grain Reconfigurable Architecture
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0002-4157-4487
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
2011 (English)In: Proceedings: 2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011, 2011, 73-80 p.Conference paper, Published paper (Refereed)
Abstract [en]

We have proposed a Dynamically Reconfigurable Resource Array (DRRA), which is a Coarse Grain Reconfigurable Architecture (CGRA). In this paper, we propose a hierarchical method for compiling DSP applications in Simulink into DRRA. In this method, each function in DRRA library can be implemented in different architecture styles and also each architectural style can be implemented in varying degrees of parallelism. Since selecting an appropriate implementation for functions of an application is very effective in performance and cost of architecture, we also formulate an optimization problem that considers implementations of functions as decision variables in order to minimize total energy consumed in the architecture under performance and cost constraints. A realistic case study exhibits up to 89% reduction of total energy consumption. It is worth mentioning that by using the proposed hierarchically compilation method, the design space is reduced dramatically while keeping the solution optimized in term of energy consumption. Hence, the optimization algorithm has low run-time complexity, enabling quick exploration of large design spaces.

Place, publisher, year, edition, pages
2011. 73-80 p.
Keyword [en]
DSP application;Simulink;architecture styles;coarse grain reconfigurable architecture;decision variables;design space;dynamically reconfigurable resource array;function implementation;hierarchical configware synthesis method;hierarchical method;optimal selection;optimization algorithm;optimization problem;run-time complexity;computational complexity;optimisation;reconfigurable architectures;
National Category
Engineering and Technology Embedded Systems
Identifiers
URN: urn:nbn:se:kth:diva-90726DOI: 10.1109/DSD.2011.14Scopus ID: 2-s2.0-80055022212OAI: oai:DiVA.org:kth-90726DiVA: diva2:506186
Conference
2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011. Oulu. 31 August 2011 - 2 September 2011
Note
QC 20120312Available from: 2012-02-28 Created: 2012-02-28 Last updated: 2012-03-12Bibliographically approved

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Li, ShuoHemani, Ahmed

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