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Power-efficient deterministic and adaptive routing in torus networks-on-chip
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2012 (English)In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 36, no 7, 571-585 p.Article in journal (Refereed) Published
Abstract [en]

Modern SoC architectures use NoCs for high-speed inter-IP communication. For NoC architectures, high-performance efficient routing algorithms with low power consumption are essential for real-time applications. NoCs with mesh and torus interconnection topologies are now popular due to their simple structures. A torus NoC is very similar to the mesh NoC, but has rather smaller diameter. For a routing algorithm to be deadlock-free in a torus, at least two virtual channels per physical channel must be used to avoid cyclic channel dependencies due to the warp-around links; however, in a mesh network deadlock freedom can be insured using only one virtual channel. The employed number of virtual channels is important since it has a direct effect on the power consumption of NoCs. In this paper, we propose a novel systematic approach for designing deadlock-free routing algorithms for torus NoCs. Using this method a new deterministic routing algorithm (called TRANC) is proposed that uses only one virtual channel per physical channel in torus NoCs. We also propose an algorithmic mapping that enables extracting TRANC-based routing algorithms from existing routing algorithms, which can be both deterministic and adaptive. The simulation results show power consumption and performance improvements when using the proposed algorithms.

Place, publisher, year, edition, pages
Elsevier, 2012. Vol. 36, no 7, 571-585 p.
Keyword [en]
Adaptive, Deadlock, Deterministic, Mesh, NoC, Performance evaluation, Power consumption, Routing, SoC, Torus, VHDL, Virtual channel
National Category
Communication Systems
URN: urn:nbn:se:kth:diva-90828DOI: 10.1016/j.micpro.2011.05.009ISI: 000309441900005ScopusID: 2-s2.0-84865838319OAI: diva2:506765

QC 20121017

Available from: 2012-02-29 Created: 2012-02-29 Last updated: 2013-12-05Bibliographically approved
In thesis
1. Performance Analysis and Design Space Exploration of On-Chip Interconnection Networks
Open this publication in new window or tab >>Performance Analysis and Design Space Exploration of On-Chip Interconnection Networks
2013 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The advance of semiconductor technology, which has led to more than one billion transistors on a single chip, has enabled designers to integrate dozens of IP (intellectual property) blocks together with large amounts of embedded memory. These advances, along with the fact that traditional communication architectures do not scale well have led to significant changes in the architecture and design of integrated circuits. One solution to these problems is to implement such a complex system using an on-chip interconnection network or network-on-chip (NoC). The multiple concurrent connections of such networks mean that they have extremely high bandwidth. Regularity can lead to design modularity providing a standard interface for easier component reuse and improved interoperability.

The present thesis addresses the performance analysis and design space exploration of NoCs using analytical and simulation-based performance analysis approaches. At first, we developed a simulator aimed to performance analysis of interconnection networks. The simulator is then used to evaluate the performance of networks topologies and routing algorithms since their choice heavily affect the performance of NoCs. Then, we surveyed popular mathematical formalisms – queueing theory, network calculus, schedulability analysis, and dataflow analysis – and how they have been applied to the analysis of on-chip communication performance in NoCs. We also addressed research problems related to modelling and design space exploration of NoCs.

In the next step, analytical router models were developed that analyse NoC performance. In addition to providing aggregate performance metrics such as latency and throughput, our approach also provides feedback about the network characteristics at a fine-level of granularity. Our approach explicates the impact that various design parameters have on the performance, thereby providing invaluable insight into NoC design. This makes it possible to use the proposed models as a powerful design and optimisation tool.

We then used the proposed analytical models to address the design space exploration and optimisation problem. System-level frameworks to address the application mapping and to design routing algorithms for NoCs were presented. We first formulated an optimisation problem of minimizing average packet latency in the network, and then solved this problem using the simulated annealing heuristic. The proposed framework can also address other design space exploration problems such as topology selection and buffer dimensioning.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2013. xxi, 37 p.
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 13:21
National Category
Computer Science
urn:nbn:se:kth:diva-136409 (URN)978-91-7501-923-9 (ISBN)
Public defence
2013-12-18, Sal/Hall D, Forum, KTH-ICT, Isafjordsgatan 39, Kista, 13:00 (English)

QC 20131205

Available from: 2013-12-05 Created: 2013-12-05 Last updated: 2013-12-05Bibliographically approved

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