Wafer-Level 3D Integration Technology Platforms for ICs and MEMS
2005 (English)In: TWENTY SECOND INTERNATIONAL VLSI MULTILEVEL INTERCONNECTION (VMIC), 2005, 486-493 p.Conference paper (Other academic)
Wafer-level three-dimensional (3D) integration is an emerging technology to increase theperformance and functionality of integrated circuits (ICs) and microelectromechanical systems(MEMS). In ICs, wafer-level 3D integration based on wafer bonding offers the potential for a highdensity of micron-sized through-die vias necessary for highest performance memory stacks,microprocessors with large L2 caches and ASICs with large embedded memories. In MEMS devices,wafer-level 3D integration based on wafer bonding offers the potential for integrating highperformance transducer materials such as various monocrystalline semiconductor materials withelectronic circuits for arrayed, highly integrated sensor and actuator components. This invited paperpresents an overview of current wafer-level 3D integration platforms that use wafer bonding withpolymer adhesives for ICs and MEMS applications.
Place, publisher, year, edition, pages
2005. 486-493 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-91418ScopusID: 2-s2.0-84888335511OAI: oai:DiVA.org:kth-91418DiVA: diva2:510018
VLSI/ULSI MULTILEVEL INTERCONNECTION CONFERENCE. Fremont, California. OCTOBER 3 - 6, 2005
QC 201203282012-03-142012-03-142012-03-28Bibliographically approved