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Wafer-Level 3D Integration Technology Platforms for ICs and MEMS
KTH, School of Electrical Engineering (EES), Microsystem Technology.ORCID iD: 0000-0002-0525-8647
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2005 (English)In: TWENTY SECOND INTERNATIONAL VLSI MULTILEVEL INTERCONNECTION (VMIC), 2005, 486-493 p.Conference paper, Published paper (Other academic)
Abstract [en]

Wafer-level three-dimensional (3D) integration is an emerging technology to increase theperformance and functionality of integrated circuits (ICs) and microelectromechanical systems(MEMS). In ICs, wafer-level 3D integration based on wafer bonding offers the potential for a highdensity of micron-sized through-die vias necessary for highest performance memory stacks,microprocessors with large L2 caches and ASICs with large embedded memories. In MEMS devices,wafer-level 3D integration based on wafer bonding offers the potential for integrating highperformance transducer materials such as various monocrystalline semiconductor materials withelectronic circuits for arrayed, highly integrated sensor and actuator components. This invited paperpresents an overview of current wafer-level 3D integration platforms that use wafer bonding withpolymer adhesives for ICs and MEMS applications.

Place, publisher, year, edition, pages
2005. 486-493 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-91418Scopus ID: 2-s2.0-84888335511OAI: oai:DiVA.org:kth-91418DiVA: diva2:510018
Conference
VLSI/ULSI MULTILEVEL INTERCONNECTION CONFERENCE. Fremont, California. OCTOBER 3 - 6, 2005
Note
QC 20120328Available from: 2012-03-14 Created: 2012-03-14 Last updated: 2012-03-28Bibliographically approved

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Niklaus, Frank

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