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Automated Topology Processing for Conventional, Phasor-Assisted and Phasor-Only State Estimators
KTH, School of Electrical Engineering (EES), Electric Power Systems.
2012 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Although the “State Estimation” concept was established decades ago, it is still a cornerstone for developing advanced applications for real-time operation and control of transmission networks. State Estimation is a key Energy Management System (EMS) function responsible of providing static estimates of the system states and line active and reactive power flows. Traditionally, state estimation uses asynchronous measurements of active and reactive power flows and voltage magnitudes, using the ICCP protocol. However, there are some novel ideas emerging recently, which suggest the usage of Phasor Measurment Unit (PMUs) that provide synchronous Measurements of positive sequence voltage and current phasors at a sample rate of up to 120 per second. The application of PMUs in power systems proliferated after the major blackouts in 2003, which revealed the critical need for wide area monitoring systems which gather data synchronously from several Phasor Measurement Units, and to give a wide area awareness of large power networks. One of the key steps at each state estimation procedure takes place is Topology Processing. Topology processing refers to the determination of the system topology through the available data from the status of the network through bus breaker status, etc. and its link to a static database which holds relevant information about the parameters of such topology. It is one the most critical steps before any other analysis can be carried out at an energy management system (EMS). At the first glance, it may seem quite easy to determine the system ’s topology:an open breaker shows that a line is disconnected. However, the problem is much more challenging when it comes to reality. Considering a real power system, there are numerous substations with different configurations, and all of those stations are connected to each other. On top of that, there may be instances when an interconnected power system is split in separate islands. The task of a network topology processor is to correctly detect these changes, and create an equivalent network model. The output of a topology processor then can be used by an EMS application, such as a state estimator. Network analysis software need to interpret the output of the topology processor and solve the associated equations related to´current topology of the network which was provided by the topology processor. To make this interpretation possible, network topology processors need to transform the bussection/switching-device model of the network into the bus/branch model. This bus/branch model then can be used for further network analysis. The work reported in this thesis encompasses development of a robust network topology processor which can be used for both traditional and PMU-based state estimators. Firstly, previous research in the field of topology processing is critically scrutinized, and the drawbacks are identified and discussed. Building on top of the state of the art an algorithm is proposed in a way to cover the limitations of current approaches and to suggest new features. The algorithm is robust enough to work with traditional data with or without PMU measurements, or to operate solely using PMU data. The topology processor was coded in MATLAB and tested over two different power networks including IEEE Reliability Test System 1996. As the topology processor is designed to supply network topologies to a PMUbased Sate Estimator, the IEEE Reliability Test System 1996 is simulated in real-time, as a bilateral work for future implementation of a complete PMU-based state estimator. Different test scenarios are performed and the voltage and current phasor outputs are extracted to emulate PMU measurements. Real-time simulation is performed using Opal-RT real-time simulator which is part of the “SmarTS Lab” at KTH Royal Institute of Technology

Place, publisher, year, edition, pages
EES Examensarbete / Master Thesis
National Category
Engineering and Technology
URN: urn:nbn:se:kth:diva-91519OAI: diva2:510596
Subject / course
Electrical Engineering
Available from: 2012-03-16 Created: 2012-03-16 Last updated: 2012-03-16Bibliographically approved

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